ds05-11235-1e fujitsu semiconduc t or d a t a sheet memory cmos 2 m 32 bits hyper p a ge mode dram module MB8502E032AA-60/-70 2m 32 bits hyper p age mode dram module , 5 v , 2-bank n description the fujitsu mb8502e032aa is a fully decoded, cmos dynamic random access memo r y (dram) module consisting of f our mb8118165a d e vice s . the mb8502e032aa is optimi z ed f or those applications requi r ing high speed, high per f o r mance and large memo r y storag e . the operation and elect r ical characte r istics of the mb8502e032aa are the same as the mb8118165a which f eatures h yper page mode operation pr o viding e xtended v alid time f or data output and higher speed random access of up to 1,024-bit of data within the same r o w than the f ast page mod e . f or ease of memo r y e xpansion, the mb8502e032aa is of f ered in a 72-pad single in-line memo r y module pa c kage (simm). n p r oduct line & fe a tures parameter MB8502E032AA-60 mb8502e032aa-70 ras acces s time 60 ns max. 70 ns max. random cycl e time 104 ns min. 124 ns min. address acces s time 30 ns max. 35 ns max. cas acces s time 15 ns max. 17 ns max. hyper p age mode cycl e time 25 ns min. 30 ns min. p o wer dissipation operating mode 1782 mw max. 1672 mw max. hyper p age mode 1122 mw max. 1012 mw max. stand b y mode 44 mw max. 44 mw max. self refresh mode 22 mw max. 22 mw max. organization : 2,097,152 w ords 32 bits memo r y : mb8118165a, 4 pcs 5.0 v 10% suppl y v oltage 1,024 refresh cycles / 16.4 ms self refresh capability hyper page mode operation (edo) p a c kage and orde r ing in f o r mation: 72-pin simm, order as mb8502e032aa- sg (sg = gold p ad)
2 MB8502E032AA-60/-70 n package (mss-72p-p85) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 dq 0 dq 1 dq 2 dq 3 v cc a 0 a 2 a 4 a 6 dq 4 dq 5 dq 6 dq 7 a 7 v cc a 9 ras 2 n.c. n.c. cas 0 cas 3 ras 0 n.c. n.c. dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 v ss dq 16 dq 17 dq 18 dq 19 n.c. a 1 a 3 a 5 n.c. dq 20 dq 21 dq 22 dq 23 n.c. a 8 ras 3 n.c. n.c. v ss cas 2 cas 1 ras 1 we dq 8 dq 9 dq 10 dq 11 dq 12 v cc pin # symbol -60 -70 67 pd 1 n.c. n.c. 68 pd 2 n.c. n.c. 69 pd 3 n.c. v ss 70 pd 4 n.c. n.c. plastic simm package
3 MB8502E032AA-60/-70 fig.1 ?block diagram dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 0 dq 1 dq 2 dq 3 lcas i/o i/o i/o i/o we ras chip2 oe i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 9 i/o i/o i/o i/o ucas cas 0 ras 1 cas 1 lcas i/o i/o i/o i/o we ras chip3 oe i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 9 i/o i/o i/o i/o ucas cas 2 ras 3 cas 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 0 dq 1 dq 2 dq 3 i/o i/o i/o i/o we chip0 i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 9 i/o i/o i/o i/o lcas ras oe ucas cas 0 ras 0 cas 1 i/o i/o i/o i/o we chip1 i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 9 i/o i/o i/o i/o lcas ras oe ucas cas 2 ras 2 cas 3 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 v cc v ss chip0 to chip3 chip0 to chip3 front side (plane0) back side (plane1) a 0 to a 9 we
4 MB8502E032AA-60/-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions (referenced to v ss ) * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n capacitance (t a = 25 c, f = 1 mhz, v cc = 5.0 v) parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out ?0 to +50 ma power dissipation p d 4w storage temperature t stg ?5 to +125 c parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ? v input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 0 70 c parameter symbol typ. max. unit input capacitance, a 0 to a 9 c in1 ?6pf input capacitance, ras 0 to ras 3 c in2 ?2pf input capacitance, cas 0 to cas 3 c in3 ?6pf input capacitance, we c in4 ?6pf i/o capacitance, (dq 0 to dq 31 )c dq ?6pf
5 MB8502E032AA-60/-70 n dc characteristics (at recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the speci? values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.3 v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc4 is speci?d at one time of address change during one page cycle. parameter notes symbol condition value unit min. max. output high voltage *1 v oh i oh = ? ma 2.4 v output low voltage *1 v ol i ol = 4.2 ma 0.4 v input leakage current ras i i(l) 0 v v in v cc , 4.5 v v cc 5.5 v, v ss = 0 v, all other pins not under test = 0 v ?0 20 m a cas ?0 20 address, we ?0 20 output leakage current i o(l) 0 v v out 5.5 v, data out disabled ?0 20 m a operating current (average power supply current) *2 MB8502E032AA-60 i cc1 ras & cas cycling, t rc = min. 324 ma mb8502e032aa-70 304 standby current (power supply current) ttl level i cc2 ras = cas = v ih ? ma cmos level ras = cas 3 v cc ?0.2 v 4 refresh current #1 (average power supply current) *2 MB8502E032AA-60 i cc3 cas = v ih , ras = cycling, t rc = min. 324 ma mb8502e032aa-70 304 hyper page mode current *2 MB8502E032AA-60 i cc4 ras = v il , cas = cycling, t hpc = min. 204 ma mb8502e032aa-70 184 refresh current #2 (average power supply current) *2 MB8502E032AA-60 i cc5 ras = cycling, cas - before-ras , t rc = min. 324 ma mb8502e032aa-70 304 refresh current #3 (average power supply current) i cc9 self refresh 4 ma
6 MB8502E032AA-60/-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter notes symbol MB8502E032AA-60 mb8502e032aa-70 unit min. max. min. max. 1 time between refresh t ref 16.4 16.4 ms 2 random read/write cycle time t rc 104 124 ns 3 access time from ras *4,7 t rac ?0?0ns 4 access time from cas *5,7 t cac ?5?7ns 5 column address access time *6,7 t aa ?0?5ns 6 output hold time t oh 3? ns 7 output hold time from cas t ohc 5? ns 8 output buffer turn on delay time t on 0? ns 9 output buffer turn off delay time *8 t off ?5?7ns 10 output buffer turn off delay time from ras *8 t ofr ?5?7ns 11 output buffer turn off delay time from we *8 t wez ?5?7ns 12 transition time t t 150150ns 13 ras precharge time t rp 40?0 ns 14 ras pulse width t ras 60 100000 70 100000 ns 15 ras hold time t rsh 15?7 ns 16 cas to ras precharge time t crp 5? ns 17 ras to cas delay time *9,10 t rcd 14 45 14 53 ns 18 cas pulse width t cas 10?3 ns 19 cas hold width t csh 40?0 ns 20 cas precharge time (normal) *17 t cpn 10?0 ns 21 row address set up time t asr 0? ns 22 row address hold time t rah 10?0 ns 23 column address set up time t asc 0? ns 24 column address hold time t cah 10?0 ns 25 column address hold time from ras t ar 24?4 ns 26 ras to column address delay time *11 t rad 12 30 12 35 ns 27 column address to ras lead time t ral 30?5 ns 28 column address to cas lead time t cal 23?8 ns 29 read command set up time t rcs 0? ns 30 read command hold time referenced to ras *12 t rrh 0? ns
7 MB8502E032AA-60/-70 (continued) no. parameter notes symbol MB8502E032AA-60 mb8502e032aa-70 unit min. max. min. max. 31 read command hold time referenced to cas *12 t rch 0? ns 32 write command set up time *13,18 t wcs 0? ns 33 write command hold time t wch 10?0 ns 34 write command hold time from ras t wcr 24?4 ns 35 we pulse width t wp 10?0 ns 36 write command to ras lead time t rwl 15?7 ns 37 write command to cas lead time t cwl 10?3 ns 38 din set up time t ds 0? ns 39 din hold time t dh 10?0 ns 40 data hold time from ras t dhr 24?4 ns 41 ras to we delay time *18 t rwd 77?9 ns 42 cas to we delay time *18 t cwd 32?6 ns 43 column address to we delay time *18 t awd 47?4 ns 44 ras precharge time to cas active time (refresh cycles) t rpc 5? ns 45 cas set up time (c-b-r refresh) t csr 0? ns 46 cas hold time (c-b-r refresh) t chr 10?2 ns 47 ras to data in delay time t rdd 15?7 ns 48 cas to data in delay time t cdd 15?7 ns 49 din to cas delay time *15 t dzc 0? ns 50 we precharge time t wpz 8? ns 51 we to data in delay time t wed 15?7 ns 52 hyper page mode ras pulse width t rasp 100000 100000 ns 53 hyper page mode read/write cycle time t hpc 25?0 ns 54 access time from cas precharge *7,16 t cpa ?5?0ns 55 hyper page mode cas precharge time t cp 10?0 ns 56 hyper page mode ras hold time from cas precharge t rhcp 35?0 ns 57 hyper page mode cas precharge to we delay time *18 t cpwd 52?9 ns 58 ras pulse width (self refresh) *19 t rass 100 100 m s 59 ras precharge time (self refresh) *19 t rps 104 124 ns 60 cas hold time (self refresh) *19 t chs ?0 ?0 ns
8 MB8502E032AA-60/-70 notes: *1. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. *2. ac characteristics assume t t = 5 ns. *3. v ih (min) and v il (max) are reference levels for measureing the timing of input signals. transition times are measured between v ih (min) and v il (max). *4. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. *5. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *6. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *7. measured with a load equivalent to two ttl loads and 100 pf. *8. t off , t oez , t ofr and t wez are speci?d that output buffer change to high-impedance state. *9. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *10. t rcd (min) = t rah (min)+ 2 t t + t asc (min). *11. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *12. either t rrh or t rch must be satis?d for a read cycle. *13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *14. assumes that t wcs < t wcs (min). *15. either t dzc or t dzo must be satis?d. *16. t cpa is access time from the selection of a new column address (caused by changing cas from ? to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max). *17. assumes that cas -before-ras refresh. *18. t wcs , t cwd , t rwd , t awd , and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state thoughout the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min), and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , t ral and t cal speci?ations. *19. assumes that self refresh. *source: see mb8118165a data sheet for details on the electricals.
9 MB8502E032AA-60/-70 n package dimensions 72-pad plastic single in-line type module (case no.: mss-72p-p85) c 1996 fujitsu limited m72086sc-1-1 1 6.350.13 (.250.005) (.080.005) 2.030.13 (3.750.002) 95.250.05 (.250.005) 6.350.13 (1.750.002) 44.450.05 (.250.001) 6.350.03 (.050.001) 1.270.03 .050 ?.003 +.004 ?0.08 +0.10 1.27 pin no1 index. (.995.005) 25.270.13 5.72(.225)min. 1.04(.041)typ. 0.25(.010)max. 2.54(.100)min. details of "a" part ? 3.180.05 (? .125.002) (3.984.004) (4.250.005) 107.950.13 101.190.10 8.89(.350)max. "a" r1.570.05 (r .062.002) r1.570.05 (r .062.002) 10.160.08 (.400.003) 72 1 72 resistor mounting area. dimensions in mm (inches)
10 MB8502E032AA-60/-70 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan
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